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6-channel sd/ed/hd video filter with charge pump ADA4424-6 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009-2010 analog devices, inc. all rights reserved. features 3 sd channels; 18 mhz typical 1 db bandwidth (bw) 3 ed/hd channels; 25 mhz or 34 mhz typical 1 db bw fixed gain of 6.2 db (2.042 v/v) on-board negative supply for output coupling without capacitors minimal dc offset at the output pins internal summation of y and c channels for cvbs output flexible input dc offset cancellation for luma channels d-terminal (eiaj rc-5237 d5) and s-terminal (s1/s2) support capable of driving 2 back-terminated 75 video loads simultaneously separate power-down pins for sd and ed/hd sections 38-lead tssop package sony green partner environmental quality approval program compliant applications dvd players and recorders set-top boxes projectors personal video recorders functional block diagram 08550-001 lpf lpf lpf lpf lpf charge pump power management s vss_sd vss_hd d/s terminal control hd_enb sd_enb +3.3 v +5v l1 l2 l3 s1/s2 l1_out l2_out l3_out s1/s2_out y_out cvbs_out c_out hy_out hpb_out hpr_out 2 2 2 1 1 c2 c1 +3.3v d1 d2 d3 y_in c_in mode0 mode1 o ffset_enb hy_in hpb_in hpr_in fc_sel sd_enable hd_enable hd_enb sd_enb 2 2 2 1 1 ADA4424-6 offset cancellation 1 vdd3_sd vdd3_hd vdd5 c1a c1b c2/cp_out vdd3_cp gnd_cp fc_sel fc_sel fc_sel figure 1. general description the ADA4424-6 is a high performance video reconstruction filter specifically designed for consumer applications. it consists of a standard definition (sd) section with two fifth-order butterworth filters and a high definition (hd) section with three fifth-order filters. the sd section contains an internal y/c summer for cvbs output, whereas the hd section provides selectable corner frequencies for either extended definition (ed) or hd signals. the ADA4424-6 filter/buffer section operates from a single 3.3 v supply. full support for d-terminal (eiaj rc-5237 d5) and s1/s2 signaling is provided, along with a dedicated 5 v supply pin. separate enable pins are provided for the sd and hd sections. the luma channels (y_in, hy_in) of the ADA4424-6 are capable of detecting and cancelling dc input offsets of up to 1.1 v. four distinct modes of detection/cancellation are available. the output drivers on the ADA4424-6 feature rail-to-rail outputs with 6.2 db gain. an on-board charge pump allows the outputs to swing up to 1.4 v below ground, eliminating the need for large coupling capacitors. each output is capable of driving two 75 doubly terminated cables. the ADA4424-6 is available in a 38-lead tssop and operates in the industrial temperature range of ?40c to +85c.
ADA4424-6 rev. c | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? maximum power dissipation ..................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ..............................................9 ? applications information .............................................................. 11 ? cvbs output .............................................................................. 11 ? corner frequency selection ..................................................... 11 ? input dc offset cancellation ................................................... 11 ? d-terminal and s-terminal support ...................................... 12 ? power-down ............................................................................... 13 ? charge pump .............................................................................. 13 ? printed circuit board (pcb) layout ....................................... 13 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 07/10rev. b to rev. c change to general description section ........................................ 1 05/10rev. a to rev. b change to table 1, overall performance ....................................... 3 change to ordering guide ............................................................ 15 12/09rev. 0 to rev. a changes to table 1 ............................................................................ 4 changes to table 2 ............................................................................ 5 changes to table 5 .......................................................................... 10 changes to table 8 to table 11 ...................................................... 11 change to table 12 and table 13 .................................................. 12 10/09revision 0: initial version
ADA4424-6 rev. c | page 3 of 16 specifications v dd3 = 3.3 v, t a = 25c, v o = 2.042 v p-p, r l = 150 , dc-coupled outputs, unless otherwise noted. charge pump configured as shown in figure 18 . table 1. parameter test conditions/comments min typ max unit overall performance dc voltage gain all channels 6.0 6.2 6.4 db input voltage range, all inputs not including dc offset ?0.6 to +1.4 v output voltage range, all outputs ?1.6 to +3.0 v input bias current y_in, hy_in, dc-coupled 30 pa input impedance c_in, hpb_in, hpr_in, ac-coupled 800 k output resistance y_out, c_out, cvbs_out, hy_out, hpb_out, hpr_out, dc-coupled 0.5 l1_out, l2_out, l3_out, s1/s2_out, dc-coupled 10.5 k sd channel dynamic performance in-band peaking f = 100 khz to 6.75 mhz 0.00 0.01 db 1 db bandwidth 14 18 mhz out-of-band rejection f = 148.5 mhz 38 42 db crosstalk f = 1 mhz 67 db total harmonic distortion f = 1 mhz, v o = 1.4 v p-p 0.07 % signal-to-noise ratio f = 100 khz to 6 mhz, unweighted 68 db group delay variation f = 100 khz to 5 mhz 1 ns differential gain ntsc 0.2 % differential phase ntsc 0.5 degrees ed channel dynamic performance fc_sel = low (0) in-band peaking f = 100 khz to 13.5 mhz 0.02 0.1 db 1 db bandwidth 21 25 mhz out-of-band rejection f = 148.5 mhz 38 42 db crosstalk f = 1 mhz 65 db total harmonic distortion f = 5 mhz, v o = 1.4 v p-p 0.45 % signal-to-noise ratio f = 100 khz to 13.5 mhz, unweighted 66 db group delay variation f = 100 khz to 13.5 mhz 1.5 ns hd channel dynamic performance fc_sel = high (1) in-band peaking f = 100 khz to 30 mhz 0.1 0.2 db 1 db bandwidth y channel (hy_out) 30 39 mhz p channels (hpb_out, hpr_out) 25 34 mhz out-of-band rejection f = 148.5 mhz 33 37 db crosstalk f = 1 mhz 65 db total harmonic distortion f = 10 mhz, v o = 1.4 v p-p 1.2 % signal-to-noise ratio f = 100 khz to 30 mhz, unweighted 65 db group delay variation f = 100 khz to 30 mhz 2.2 ns dc characteristics operating voltage, 3.3 v supply 3.14 to 3.46 v quiescent supply current, 3.3 v supply both active, sd_enable = high, hd_enable = high, no load, no signal, not including d/s terminal outputs 93 133 ma sd disabled, sd_enable = low, hd_enable = high 54 ma hd disabled, sd_enable = high, hd_enable = low 45 ma both disabled, sd_enable = low, hd_enable = low 6.1 10 ma operating voltage, 5 v supply 4.75 to 5.25 v
ADA4424-6 rev. c | page 4 of 16 parameter test conditions/comments min typ max unit quiescent supply current, 5 v supply sd_enable = high, hd_enable = high, r l = 100 k, d1, d2, d3 = high, s = high 190 200 a sd_enable = low, hd_enable = low 5 15 a psrr ed/hd channels, outp ut referred ?42 db sd channels, output referred ?41 db dc offset see table 6 and table 7 input referred, offset cancellation disabled mode offset_enb = low sd channels y_in = 0 v dc ?60 ?20 +60 mv cvbs channel y_in = 0 v dc ?100 ?40 +100 mv ed/hd channels hy_in = 0 v dc ?60 ?20 +60 mv input referred, fixed offset cancellation mode offset_enb = high, mode1 = high sd fixed high offset mode y_in = 1.0 v dc, mode0 = low ?100 ?30 +100 mv ed/hd fixed high offset mode hy_in = 1.1 v dc, mode0 = low ?100 ?38 +100 mv sd fixed low offset mode y_in = 0.33 v dc, mode0 = high ?90 ?17 +90 mv ed/hd fixed low offset mode hy_in = 0.33 v dc, mode0 = high ?100 ?25 +100 mv input referred, auto offset cancellation mode offset_enb = high, mode1 = low sd auto offset mode sync tip sampling y_in = 0 v to 1.0 v dc, mode0 = low ?70 ?36 +70 mv ed/hd auto offset mode sync tip sampling hy_in = 0 v to 1.1 v dc, mode0 = low ?95 ?46 +95 mv sd auto offset mode back porch sampling y_in = 0 v to 1.0 v dc, mode0 = high ?25 ?6 +25 mv ed/hd auto offset mode back porch sampling hy_in = 0 v to 1.1 v dc, mode0 = high ?25 ?5 +25 mv fc_sel input logic low level 0 0.6 v fc_sel input logic high level 1.2 v dd3 v xd_enable, offset_enb, modex input logic low level 0 0.8 v xd_enable, offset_enb, modex input logic high level 2.0 v dd3 v xd_enable assert time xd_enable = low to high 95 ns xd_enable deassert time xd_enable = high to low 20 ns xd_enable input bias current disabled, xd_enable = low 6.1 a input-to-output isolation disabled, xd_enable = low, f = 5 mhz ?100 db d- and s-terminal input logic low level r l = 100 k 0 0.6 v d- and s-terminal input logic mid level r l = 100 k 0.9 1.9 v d- and s-terminal input logic high level r l = 100 k 2.7 v dd3 v d- and s-terminal input logic open (hi-z) resistance value r l = 100 k 200 k d-terminal (l1_out, l2_out, l3_out) low level output v dd5 = 5.0 v, r l = 100 k, d1, d2, d3 = low 0.0 v d-terminal (l1_out, l3_out) mid level output v dd5 = 5.0 v, r l = 100 k, d1, d3 = mid or open 2.1 v d-terminal (l1_out, l2_out, l3_out) high level output v dd5 = 5.0 v, r l = 100 k, d1, d2, d3 = high 4.5 v s-terminal (s1/s2_out) low level output v dd5 = 5.0 v, r l = 100 k, s = low 0.0 v
ADA4424-6 rev. c | page 5 of 16 parameter test conditions/comments min typ max unit s-terminal (s1/s2_out) mid level output v dd5 = 5.0 v, r l = 100 k, s = mid or open 2.1 v s-terminal (s1/s2_out) high level output v dd5 = 5.0 v, r l = 100 k, s = high 4.5 v charge pump characteristics all channels operating; c1 = c2 = 4.7 f, c3 = c4 = 1.0 f, r1 = 1 (see figure 18 ) output voltage ?1.66 v output voltage ripple 180 mv p-p output ripple frequency 100 khz
ADA4424-6 rev. c | page 6 of 16 absolute maximum ratings table 2. parameter rating 3.3 v supply voltage 3.6 v 5 v supply voltage 5.5 v digital input voltage (pin 2 to pin 5, pin 8, pin 12, pin 15, pin 16, pin 23) 3.6 v power dissipation see figure 2 storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to load drive depends on the particular application. for each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. the power dissipated due to the loads is equal to the sum of the power dissipations due to each individual load. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . figure 2 shows the maximum power dissipation in the package vs. the ambient temperature for the 38-lead tssop (67.6c/w) on a jedec standard 4-layer board. ja values are approximate. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.4 0 0 100 ambient temperature (c) maximum power dissipation (w) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 10 20 30 40 50 60 70 80 90 08550-002 thermal resistance ja is specified for the device soldered to a high thermal conductivity 4-layer (2s2p) circuit board, as described in eia/jesd 51-7. table 3. package type ja jc unit 38-lead tssop 67.6 14.0 c/w maximum power dissipation figure 2. maximum power dissipation vs. ambient temperature for a 4-layer board the maximum safe power dissipation in the ADA4424-6 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4424-6. exceeding a junction temperature of 150c for an extended time can result in changes in the silicon devices, potentially causing failure. esd caution
ADA4424-6 rev. c | page 7 of 16 pin configuration and fu nction descriptions d1 d2 d3 vdd3_sd y_in s gnd5 sd_enable c_in gnd3 hpr_in fc_sel hy_in hpb_in hd_enable c1a offset_enb mode0 vdd3_cp l1_out l2_out l3_out vss_sd y_out s1/s2_out cvbs_out c_out gnd3 hpr_out hpb_out vss_hd hy_out vdd3_hd gnd_cp c1b c2/cp_out mode1 vdd5 ADA4424-6 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 08550-003 figure 3. pin configuration, top view table 4. pin function descriptions pin o. mnemonic description 1 gnd5 ground pin for 5 v supply. 2 d1 d-terminal vertical resolution selection input. 3 d2 d-terminal scan selection input. 4 d3 d-terminal aspect ratio selection input. 5 s s-terminal aspect ratio selection input. 6 y_in sd luma (y) input. 7 vdd3_sd 3.3 v supply pin for sd filter section. 8 sd_enable output enable pin for sd (y, c, cvbs). 9 c_in sd chroma (c) input. 10, 29 gnd3 ground pins for 3.3 v supply. 11 hy_in ed/hd y component input. 12 fc_sel filter corner frequency selection pin for hy, hpb, hpr channels. 13 hpb_in ed/hd pb component input. 14 hpr_in ed/hd pr component input. 15 hd_enable output enable pin for ed/hd (hy, hpb, hpr). 16 mode0 this pin selects sync tip or back porch sampling when mode1 = 0 and selects high or low fixed offset subtraction when mode1 = 1. 17 offset_enb offset cancellation enable pin. 18 vdd3_cp 3.3 v supply pins for charge pump section. 19, 21 c1a, c1b charge pump capacitor c1 connection pin. 20 gnd_cp ground pin for 3.3 v charge pump supply. 22 c2/cp_out charge pump output pin. connect capacitor c2 from this pin to ground. 23 mode1 selects automatic or fixed offset subtraction mode. 24 vdd3_hd 3.3 v supply pin for ed/hd filter section. 25 hpr_out ed/hd pr component output. 26 hpb_out ed/hd pb component output. 27 vss_hd negative supply pin for ed/hd filter section. this pin should be connected to the charge pump output (pin 22), as shown in figure 18 . 28 hy_out ed/hd y component output. 30 c_out sd chroma (c) output. 31 cvbs_out sd composite video (cvbs) output.
ADA4424-6 rev. c | page 8 of 16 pin no. mnemonic description 32 vss_sd negative supply pin for sd filter section. this pin shou ld be connected to the charge pump output (pin 22), as shown in figure 18 . 33 y_out sd luma (y) output. 34 s1/s2_out s-terminal aspect ratio selection output. 35 l3_out d-terminal aspect ratio selection output. 36 l2_out d-terminal scan selection output. 37 l1_out d-terminal vertical resolution selection output. 38 vdd5 5 v supply pin for d-terminal and s-terminal signaling.
ADA4424-6 rev. c | page 9 of 16 typical performance characteristics v dd3 = 3.3 v, t a = 25c, v o = 2.042 v p-p, r l = 150 , dc-coupled outputs, unless otherwise noted. charge pump configured as shown in figure 18 . 10 ?60 0.1 frequency (mhz) normalized gain (db) 11 01 0 0 0 ?10 ?20 ?30 ?40 ?50 y cvbs c 08550-004 figure 4. frequency responsesd channels 0.1 1k frequency (mhz) normalized gain (db) 1 10 100 hy pb pr 10 ?60 0 ?10 ?20 ?30 ?40 ?50 08550-005 figure 5. frequency responseed channels 10 ?60 0.1 1k frequency (mhz) normalized gain (db) 1 10 100 0 ?10 ?20 ?30 ?40 ?50 pr pb hy 08550-006 figure 6. frequency responsehd channels 0.5 ?1.0 0.1 100 frequency (mhz) normalized gain (db) 11 0 0 ?0.5 c y/cvbs 08550-007 figure 7. frequency response peakingsd channels 0.5 ?1.0 0.1 100 frequency (mhz) normalized gain (db) 11 0 0 ?0.5 hy pr pb 08550-008 figure 8. frequency response peakinged channels 0.5 ?1.0 0.1 100 frequency (mhz) normalized gain (db) 11 0 0 ?0.5 hy pb/pr 08550-009 figure 9. frequency response peakinghd channels
ADA4424-6 rev. c | page 10 of 16 ? 20 ?80 0.1 100 frequency (mhz) crosstalk (db) 11 0 ?30 ?40 ?50 ?60 ?70 all hostile referred to input cvbs_out y_out c_out 08550-010 figure 10. crosstalksd channels 45 0 0.1 100 frequency (mhz) group delay (ns) 11 0 40 35 30 25 20 15 10 5 y_out, c_out cvbs_out 08550-011 figure 11. group delaysd channels 45 0 0.1 100 frequency (mhz) group delay (ns) 11 0 40 35 30 25 20 15 10 5 08550-012 figure 12. group delayhd channels ? 20 ?80 0.1 100 frequency (mhz) crosstalk (db) 11 0 ?30 ?40 ?50 ?60 ?70 all hostile referred to input hpb_out, hpr_out hy_out 08550-013 figure 13. crosstalked and hd channels 45 0 0.1 100 frequency (mhz) group delay (ns) 11 0 40 35 30 25 20 15 10 5 08550-014 figure 14. group delayed channels ? 40 ?120 0.1 100 frequency (mhz) input-to-output isolation (db) 11 0 ?50 ?60 ?70 ?80 ?90 ?100 ?110 v in = 1.0v p-p r l = 150 ? sd_enable = 0 hd_enable = 0 08550-015 figure 15. input-to-output isolationall channels
ADA4424-6 rev. c | page 11 of 16 applications information cvbs output the composite video signal (cvbs_out) is produced by passively summing the y and c channels (see figure 1), after amplification by their respective gain stages. each signal experiences a 6.2 db loss from the passive summation and is subsequently amplified by 6.2 db in the fixed stage following the summer. the net signal gain through the composite video path is, therefore, 0 db, and the resulting composite signal present at the ADA4424-6 output is the sum of y and c with unity gain. corner frequency selection the component channels of the ADA4424-6 allow for a 1 db filter corner frequency of either 25 mhz or 39 mhz/34 mhz. the fc_sel pin operates as described in table 5 . table 5. ed/hd bandwidth selection fc_sel (pin 12) hd/ed ?1 db corner frequency (typ) low (0) ed 25 mhz high (1) hd 39 mhz (hy); 34 mhz (pb, pr) input dc offset cancellation the luma channels (y_in, hy_in) of the ADA4424-6 are capable of detecting and cancelling dc input offsets of up to 1.1 v. four distinct modes of detection/cancellation are available. these are selected via the mode1 and mode0 pins. the chroma (c_in) and color difference (hpb_in, hpr_in) inputs do not support offset cancellation. it is recommended that these inputs be ac- coupled. automatic detection/cancellation mode there are two modes of automatic operation. the primary mode samples the input signal between the rising edge of the horizon- tal sync pulse and the start of active video (back porch), averages the value over the sampling interval, and subtracts it from the output signal. this is the more accurate method and is able to reduce the input-referred offsets to less than 25 mv. an alternate method is available for copy-protected signals, where sampling the back porch may not provide a reliable dc average. this method detects the input negative sync tip, and clamps it to a fixed value (?214 mv for sd, and ?300 mv for ed/hd). sample intervals for sd and ed are shown in figure 16 , and the hd sample intervals are shown in figure 17 . black level sync tip sample interval back porch sample interval 0 8550-017 figure 16. back porch and sync tip sample intervals (sd/ed) black level sync tip sample interval back porch sample interval 08550-018 figure 17. back porch and sync tip sample intervals (hd)
ADA4424-6 rev. c | page 12 of 16 fixed offset cancellation mode in addition to the automatic mode, there are two levels of fixed offset correction available. in high offset mode, fixed voltages of 1.0 v and 1.1 v are subtracted from the y_in and hy_in inputs, respectively. in low offset mode, a fixed voltage of 0.33 v is subtracted from both y_in and hy_in. the various modes of offset cancellation are outlined in table 6 . table 6. offset cancellation mode selection mode1 (pin 23) mode0 (pin 16) output offset cancellation low (0) low (0) auto-cancel, sync-tip sampling mode. clamps the input referred sd sync tip to ?214 mv, and the input referred ed/hd sync tip to ?300 mv. low (0) high (1) auto-cancel, back porch sampling mode. sets the output blanking level to 0 v, independent of sync depth. high (1) low (0) fixed cancellation mode, high dc offset. subtracts 1.0 v from the y_in signal; subtracts 1.1 v from the hy_in signal. high (1) high (1) fixed cancellation mode, low dc offset. subtracts 0.33 v from both the y_in and hy_in signals. offset cancellation disable the offset cancellation function can be enabled or disabled via the offset_enb pin, as described in table 7 . table 7. offset cancellation enable/disable offset_enb (pin 17) offset cancellation state low (0) offset cancellation is disabled. high (1) offset cancellation is enabled. function is determined by the mode1 and mode0 pins (see table 6 ). d-terminal and s-terminal support full d-terminal support (eiaj rc-5237 d5) is provided for the component channels (hy_out, hpb_out, hpr_out). level d1 through level d5 are supported for vertical resolution, scan type, and aspect ratio selection. details are shown in table 8 , table 9 , and table 10 . s-terminal (also known as s_dc or s1/s2) support for s-video aspect ratio selection is also provided, as described in table 11 . the vdd5 pin (pin 38) provides 5 v power for these outputs. if d- or s-terminal support is not required, it is recommended that pin 2 to pin 5 and pin 34 to pin 38 remain unconnected. table 8. d-terminal control for vertical resolution selection input logic level d1 (pin 2) nominal output (v) l1_out (pin 37) r l = 100 k vertical resolution (number of lines) low (0) 0.0 480 mid or open 2.1 720 high (1) 4.5 1080 table 9. d-terminal control for scan selection input logic level d2 (pin 3) nominal output (v) l2_out (pin 36) r l = 100 k scan type low (0) 0.0 interlaced mid or open 2.1 n/a high (1) 4.5 progressive table 10. d-terminal control for aspect ratio selection input logic level d3 (pin 4) nominal output (v) l3_out (pin 35) r l = 100 k aspect ratio low (0) 0.0 4:3 mid or open 2.1 4:3 letterbox high (1) 4.5 16:9 table 11. s-terminal control for aspect ratio selection input logic level s (pin 5) nominal output (v) s1/s2_out (pin 34) r l = 100 k aspect ratio low (0) 0.0 4:3 mid or open 2.1 4:3 letterbox high (1) 4.5 16:9
ADA4424-6 rev. c | page 13 of 16 power-down the ADA4424-6 provides separate output enable pins for the sd and ed/hd sections. in addition to powering down the y, c, and cvbs outputs, the sd_enable pin, when driven low, also places the s1/s2 output (s1/s2_out, pin 34) in a high impedance state. likewise, driving the hd_enable pin low disables the component outputs (hy_out, hpb_out, and hpr_out) and changes the l1, l2, and l3 outputs (lx_out, pin 35 to pin 37) to a high impedance state. control details are shown in table 12 and table 13 . table 12. power-down control for sd channels sd_enable (pin 8) sd outputs (y, c, cvbs) s1/s2_out (pin 34) low (0) disabled high-z (open) high (1) enabled active table 13. power-down control for ed/hd channels hd_enable (pin 15) ed/hd outputs (hy, hpb, hpr) lx_out (pin 35, pin 36, pin 37) low (0) disabled high-z (open) high (1) enabled active charge pump the ADA4424-6 features an on-chip charge pump that supplies a negative rail voltage for the output stages. to minimize internal noise coupling, the charge pump uses an external connection to the negative supply pins (vss_sd and vss_hd). these pins should be connected to the c2/cp_out pin, each decoupled with a 1.0 f capacitor. it is also recommended to place a small (1 ) series resistor in this connection. this forms a low-pass filter with the vss decoupling capacitors and further reduces coupled noise. the charge pump also requires two 4.7 f ceramic capacitors, one connected across the c1a and c1b pins, and one connected from the c2/cp_out pin to ground. the recom- mended charge pump configuration is shown in the application diagram ( figure 18 ). with the black or zero level of the outputs placed at approx- imately ground potential, the outputs can swing up to 1.6 v in the negative direction. this eliminates the need for large output coupling capacitors because the input-referred dc offsets does not exceed 100 mv (depending on the selected cancellation mode). printed circuit board (pcb) layout as with all high speed applications, attention to the pcb layout is of paramount importance. when designing with the ADA4424-6, adhere to standard high speed layout practices. a solid ground plane is recommended, and surface-mount, ceramic power supply decoupling capacitors should be placed as close as possible to the supply pins. connect all of the ADA4424-6 gnd pins to the ground plane with traces that are as short as possible. controlled impedance traces of the shortest length possible should be used to connect to the signal i/o pins and should not pass over any voids in the ground plane. a 75 impedance level is typically used in video applications. when driving transmission lines, include series termination resistors on the signal outputs of the ADA4424-6.
ADA4424-6 rev. c | page 14 of 16 video encoder 75 ? 75 ? 75? 75? 75? 75? pr pb y cvbs charge pump rset2 rset1 +3.3 v 10f offset_enb mode0 mode1 y_in c_in 100nf sd_enable vdd3_sd 1.0f 1.0f 1.0f hy_in hpb_in hpr_in fc_sel hd_enable vdd3_hd vdd3_cp +3.3v c1a c1b c1 4.7f c2 4.7f gnd_cp c2/cp_out r1 1.0 ? c4 1.0f vss_hd gnd3 hpr_out hpb_out hy_out c3 1.0f vss_sd gnd3 c_out cvbs_out y_out s-video lpf lpf x2 x2 x2 x1 lpf x2 x1 lpf x2 x1 lpf x2 x1 x1 ADA4424-6 dac1 dac2 dac3 dac4 dac5 + 1.0f 1.0f 08550-019 figure 18. typical application diagram for using the ADA4424-6 in auto offset cancellation mode (d and s terminal connections not shown)
ADA4424-6 rev. c | page 15 of 16 outline dimensions 38 20 19 1 9.80 9.70 9.60 pin 1 seating plane 0 .15 0 .05 0.50 bsc 0.27 0.17 1.20 max 0.20 0.09 8 0 4.50 4.40 4.30 6.40 bsc 0.70 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153-bd-1 figure 19. 38-lead thin shrink small outline package [tssop] (ru-38) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity ADA4424-6aruz ?40c to +85c 38-lead thin shrink small outline package (tssop) ru-38 50 ADA4424-6aruz-r7 ?40c to +85c 38-lead thin sh rink small outline package (tssop) ru-38 1,000 ADA4424-6aruz-rl ?40c to +85c 38-lead thin sh rink small outline package (tssop) ru-38 2,500 1 z = rohs compliant part.
ADA4424-6 rev. c | page 16 of 16 notes ?2009-2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08550-0-7/10(c)

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